This invention relates to the fabrication of integrated circuit gate structures, and more particularly to a method for making a self-aligned, nonoverlapping gate structure for a charge coupled device (CCD).
An ideal gate structure for a CCD has a series of elongated, narrow conductors formed on the surface of a semiconductor substrate in alignment with underlying, doped charge-storage regions. The conductors are closely spaced but separated by a thin, insulative layer or dielectric. Ideally, the adjacent conductors do not overlap. In practice, however, conventional fabrication techniques cannot assure perfect alignment of the gate electrodes to avoid discontinuities in the gate structure. Alignment becomes even more difficult as device dimensions are reduced, for example, to increase resolution in optical CCDs.
Consequently, most commercially available CCD are fabricated with an overlapping gate structure, for example, as shown in FIG. 1 of U.S. Pat. No. 4,319,261 to Kub. It is recognized that such devices exhibit overlap capacitance, which can be disadvantageous in their operation for many applications. Employing such an overlap also limits the ability to reduce device size. A practical limit to gate width, using conventional photolithographic techniques is 4 .mu.m., and using electron beam technology is about 2 .mu.m. Another drawback is that overlapping gate designs are prone to shorting along the overlap. This problem limits operative device yields and makes wafer-scale integration almost impossible.
Various proposals have been made to fabricate nonoverlapping gate structures in CCDs. The aforementioned patent to Kub suggests forming alternate, doped polysilicon gate conductors at different elevations from the substrate surface. The elevated gates are spaced from the substrate and the adjacent, non-elevated conductors by a thickness of undoped polysilicon. U.S. Pat. No. 4,461,070 to Cline applies thin film lamellar metallic eutectic gates, and selectively removes one of the eutectic phases to form one of the spaced gate arrays. After applying an insulative layer, another conductive layer is applied and etched to form the intervening gates. Some overlap results in this process.
U.S. Pat. Nos. 4,351,100 and 4,352,237 to Widmann disclose two related but different self-adjusting, nonoverlapping CCD gate processes as follows: a first polysilicon layer is deposited and covered with a layer of silicon dioxide. These layers are patterned and etched to form spaced poly-Si-1 electrodes that are initially somewhat larger than their final width. Then, the first polysilicon layer is undercut beneath the silicon dioxide cover to produce pairs of confronting SiO.sub.2 overhangs with gaps therebetween. Oxidizing provides an insulating layer at the end faces of the poly-Si-1 electrodes. Then, a second polysilicon layer is applied by chemical vapor deposition (CVD) so as to fill the cavities beneath the two overhangs. Any excess polysilicon deposited atop the SiO.sub.2 cover layer is then etched away so as to leave the intervening self adjusting, nonoverlapping poly-Si-2 electrodes.
One drawback in the process of Widmann U.S. Pat. No. 4,352,237 is that it requires very small gap geometry, 1.6 to 1.8 .mu.m. gap width. It will not provide a planar poly-Si-2 layer if the gap is too wide, e.g., 3 .mu.m. Consequently, it cannot be used in large-sized imagers which are needed in situations requiring large dynamic range and low noise, such as astronomy. It also cannot be used in a three-layer polysilicon--3-phase process. The process of Widmann U.S. Pat. No. 4,351,100 is vulnerable to alignment inaccuracies and, therefore, would not increase yields over devices made by conventional techniques.
Accordingly, a need remains for a satisfactory method of making nonoverlapping gate structures for CCDs and other semiconductor devices.